Lead routing between Integrated Circuits (IC's) on a Printed Circuit (PC) board plays an important role in both the cost and the performance of the PC board design. The cost of manufacturing a PC board is directly related to the number of layers required to effectively route all of the leads between the IC's. The ability to reduce the number of leads, match the length of leads and the potential for interference between leads enhances the performance of the PC board. As the IC density on PC boards increase and the number of pin assignments and associated leads per IC go up, lead routing becomes increasingly more difficult.
In the mid-80's, surface mount technology (SMT) and double sided SMT were introduced as an alternative to standard through-hole PC board technology. Instead of pre-drilling PC boards to accept the pins of IC's, special packaging for IC's was developed which provided for gluing IC's to the PC board. Since the requirement for sticking pins through to the opposite side of the PC board and soldering the IC's in place was eliminated, it became possible to mount IC's on both sides of the PC board.
Even though SMT provides for increased efficiency in lead routing, problems still exist as the total number of IC's on the PC board doubles with two-sided SMT. The number of leads required to interconnect IC's goes up with both the total number of IC's on the PC board, as well as with advances in Very Large Scale Integration (VLSI) design (up to 1,000,000 components may now be integrated into a single IC). A standard 1 megabyte memory chip has 44 pin assignments, a custom memory controller chip may have over 200 pin assignments, and a multichip module (MCM) which approaches 2.5 centimeters square may have over 500 pin assignments.
The layout of a circuit board generally proceeds from the circuit diagram to a geometric layout in which IC's are grouped in their respective isolation regions. Leads coupling IC's are laid out to eliminate potential lead crossovers. Lead routing is a three dimensional problem and becomes very complex with high chip and associated lead densities. Lead crossovers are typically eliminated by adding additional layers to the circuit board such that leads can be re-routed through vias to different levels. Via is the term used to describe a hole partially through the circuit board which enables a lead to travel from one board level to another. Additionally, lead routing is made even more complex as constraints such as maximum length and a consistency between lead lengths must be provided for.
As circuit speeds increase the distributed capacitance and inductance over the length of each lead causes it to act like transmission lines. Reduction of the overall lead length reduces adverse electronic emissions from the circuit board. Crosstalk (an undesirable coupling between an active line and an adjacent passive line) may occur do to mutual inductance or capacitance. Crosstalk can also cause a loss of signal strength in the active line, and interference or false triggering in an adjacent line. Lateral crosstalk may occur when adjacent leads are located on the same plane. Leads located on opposite sides of a dielectric laminate may result in vertical crosstalk. Crosstalk can be minimized by increasing the distance between adjacent leads or reducing the length of parallel lead sections. Vertical crosstalk can be virtually eliminated by orthogonal routing of leads on adjacent layers.
In circuit boards incorporating more than one IC of the same type, circuit board complexity, problems associated with crossover and crosstalk, can be minimized by utilizing pairs of integrated circuits designed with two identical but reversed pin assignments. As illustrated in FIG. 1, an eight MBIT Flash memory sold by Intel (F28F008SA) is offered in both a standard pin assignment (FIG. 1A) and a reversed pin assignment (FIG. 1B) configuration. By alternating the memory chips in a serpentine layout (FIG. 2), the reversed pin assignment provides for a greatly simplified board layout as crossovers and the length of the interconnecting leads are minimized. Unfortunately, two different IC's must be manufactured and proper placement on the PC board necessitates subsequent identification during IC insertion.
Another example of the prior art is disclosed in U.S. Pat. No. 5,270,964 issued Dec. 14, 1993 to Bechtolsheim et al. Bechtolsheim discloses a single in-line memory module (SIMM) having two hundred pin assignments. A high number density connector is used to connect the SIMM to a memory module socket on a PC board. All power and ground leads are symmetrically arranged within the connector. Power and ground leads alternate every sixteen pins such that if the SIMM is inadvertently inserted in a reversed position into the memory module socket, the symmetrical power and ground leads prevent the SIMM from being reverse-powered, and likely destroyed.
There is accordingly a need to provide for simplified lead routing and the reduction of the number of layers in the PC board required to accommodate the demands of high density IC's and multichip modules having hundreds of pin assignments.